A road named NoNameUno

I was recently trying to dig deep into PCI/PCI-X/PCI-e. Basic concept of interruption is known to most of us. It is asynchronous events to get attention of the CPU(s). In older days, there is pin on the CPU, a device asserts the PIN, and CPU checks on instruction boundary, if a device need attention, and proceed accordingly based on the priority. When it comes to electronics, real estate is not cheap, but we the hungry people wants more and more devices to be attached to our base gadgets. So naturally there are interrupt sharing, interrupt delivery, and interrupt priorities came into design process. As old news is no news, excessive delays to service interrupt is no service. So that was the start of PIC, programmable interrupt controller. Then came multi processors, and interrupt delivery to specific subsets of the processors. And IOAPIC was born. In its primitive form, an interrupt could be broadcasted to all the processor, and depending on the mask a processor will either ack it or ignore it depending on the policies. Some time this is in the area of APIC bus technology. Finally ( as of now ) came message based interruption as opposed to the older line based interrupt. The idea is to have lots of different types of interrupts to be served by a set of processors. In the older line based interrupt there were two main steps:Interrupt Ack, and receiving the vector index so that OS can jump off to the service routine and serve the interrupt. From the HW point of view at a higher level it is two step process. For MSI-X, the story is quite different, and somewhat not so well documented ... The PCI specs, and the Mindshare books ( PCI Arch, PCI-X, and PCI-E ) does not spell out the sequence of events and the corresponding handlers at the HW level to service interrupts. We see how the configuration space has been primed. We see how the device uses MSI address register, and data register to signal ( or to be precise do a WR PCI post transaction ). But how does it get to CPU? When does a CPU know that an interrupt is pended, stop whatever is being done and go for servicing the interrupt. Well, read on those books and let me know if there is a clear way it has been described... But if WEB is your friend, well it is not my friend since walking outside often gives me trouble while bumping on invisible spider webs, you can search and get some hints. Basically when the transaction is posted into some specific location (yeah, hand waving here ), some component of Root complex or some other chipset knows that it is not a regular PCI WR transaction, it is an MSI-X write (WR) transaction, so it tries to get the CPUs attention. There are ICR (interrupt control registers), and that comes into play... So basically few things are important - 1) When a device writes a PCI-X posted transaction, who lets the CPU know an interrupt has arrived, and how does it do it? 2) When does the CPU go check if an interrupt attention has happend? It is still at instruction boundary! 3) When does it know an interrupt attention is pending, where does it get the index from to vector into the MSI-x interrupt vector table?